For many years the SST1 and SST2 architecture has intrigued me, especially because it is so weird compared to all the other contemporary graphics system architectures (single chip 2D/3D).
That is why I have decided to sand down the pcb of a (COMPLETELY BROKEN) voodoo 2, below is a snapshot of the (only) inner layer signal path, all other inner layers are planes. I scanned all layers at a decent resolution with a flatbed scanner.
[Blockierte Grafik: http://i.imgur.com/uGdD0KM.jpg]
The goal is to create a complete schematic of the entire pcb to understand more about how the voodoo 2 works, and find out what is possible concerning memory upgrades. If people are interested I will update this thread with some information when I find out more.
Update 16/7:
I have traced all of the address pins (red) from the ram chips to a Bruce IC(TMU) , as you can see there are 36 pins which adds up to 4MB addressable memory space. So if Chuck supports 8MB memory it is very likely that four of the cream colored pins (they go to ground) are unused address pins. The other option would be four way interleaving which is pretty unlikely.
Explanation: 9 address pins per memory ic means: 2^9 * 2^9 * 16bit = 524288Kbyte there are 36 address pins and two memory banks (two different RAS lines), so this adds up to 512Kbyte * 4 *2 = 4Mbyte. So for 8MB addressable memory 40 pins are required!
[Blockierte Grafik: http://i.imgur.com/ThQHKXI.jpg]
If I seem to be wrong somewhere please correct me!
Update 1/8/16:
Part List finished. Certain values can differ among cards, the difference is not significant 120nF instead of 100nF. They are simply bypass capacitors for the supply pins.
Update 4/8/16:
Found out I decapped the Chuck chip back in the day (the sanding method) just to have a look. The die size is about 50mm2, and I found 66 bond wires on each side. Hopefully the chip is not damaged too much to still make a die shot out of it. Will have to try to x-ray 'enclosed' Bruce and Chuck chips to find out more about the bond wires.
